A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm

A flexible floating-point logarithm for reconfigurable computers

The advent of reconfigurable co-processors based on field-programmable gate arrays has renewed interest in hardware architectures for elementary functions. This article studies operators for the logarithm function in the context of this target technology. An old algorithm is generalized, fine-tuned and implemented as an architecture generator, exposing a wide range of trade-offs between resourc...

The Unified Floating Point Vector Co-processor for Reconfigurable Hardware

There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more hom...

The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

A Floating-Point Unit for Arithmetic Operations

In this paper we present a design for a floating point unit partially compliant with the IEEE 754 floating point standard. The unit fully implements comparisons and partially implements floating-point addition and multiplication. It is fully parametrized and may be used with floating point numbers whose composite fields have widths of any desired length.

Reconfigurable Custom Floating-Point Instructions

Multimedia and communication algorithms from the embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floatingpoint hardware, these algorithms are usually converted to fixed point operations, or implemented using floating-point emulation in software. This study presents the design and implementation of custom floating-point units...